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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516CD641ES, 4516CD641PS
16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
The MC-4516CD641ES and MC-4516CD641PS are 16,777,216 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on which 8 pieces of 128M SDRAM: PD45128163 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 16,777,216 words by 64 bits organization * Clock frequency and access time from CLK
Part number MC-4516CD641ES-A80 /CAS latency CL = 3 CL = 2 MC-4516CD641ES-A10 CL = 3 CL = 2 Clock frequency (MAX.) 125 MHz 100 MHz 100 MHz 77 MHz 125 MHz 100 MHz 100 MHz 77 MHz Access time from CLK (MAX.) 6 ns 6 ns 6 ns 7 ns 6 ns 6 ns 6 ns 7 ns
5 5
MC-4516CD641PS-A80
CL = 3 CL = 2
MC-4516CD641PS-A10
CL = 3 CL = 2
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Quad internal banks controlled by BA0, BA1 (Bank Select) * Programmable burst-length (1, 2, 4, 8 and Full Page) * Programmable wrap sequence (Sequential / Interleave) * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * Single 3.3 V 0.3 V power supply * LVTTL compatible * 4,096 refresh cycles/64 ms * Burst termination by Burst Stop command and Precharge command * 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm) * Unbuffered type * Serial PD
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14014EJ5V0DS00 (5th edition) Date Published February 2000 NS CP(K) Printed in Japan
The mark * shows major revised points.
(c)
1999
MC-4516CD641ES, 4516CD641PS
Ordering Information
Part number Clock frequency MHz (MAX.) MC-4516CD641ES-A80 125 MHz 144-pin Small Outline DIMM (Socket Type) MC-4516CD641ES-A10 100 MHz Edge connector: Gold plated 31.75 mm height 8 pieces of PD45128163G5 (Rev. E) (10.16mm (400) TSOP(II)) Package Mounted devices
5
MC-4516CD641PS-A80
125 MHz
8 pieces of PD45128163G5 (Rev. P) (10.16mm (400) TSOP(II))
5
MC-4516CD641PS-A10
100 MHz
2
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
Vss DQ 32 DQ 33 DQ 34 DQ 35 Vcc DQ 36 DQ 37 DQ 38 DQ 39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ 40 DQ 41 DQ 42 DQ 43 Vcc DQ 44 DQ 45 DQ 46 DQ 47 Vss NC NC
Vss DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 Vss DQMB0 DQMB1 VCC A0 A1 A2 Vss DQ 8 DQ 9 DQ 10 DQ 11 VCC DQ 12 DQ 13 DQ 14 DQ 15 Vss NC NC
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
/xxx indicates active low signal.
62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
CLK0 CKE0 Vcc Vcc /RAS /CAS /WE CKE1 /CS0 NC /CS1 NC NC CLK1 Vss Vss NC NC NC NC VCC Vcc DQ 16 DQ 48 DQ 17 DQ 49 DQ 18 DQ 50 DQ 19 DQ 51 Vss Vss DQ 20 DQ 52 DQ 21 DQ 53 DQ 22 DQ 54 DQ 23 DQ 55 Vcc Vcc A6 A7 A8 BA0 (A13) Vss Vss A9 BA1 (A12) A10 A11 Vcc Vcc DQMB2 DQMB6 DQMB3 DQMB7 Vss Vss DQ 24 DQ 56 DQ 25 DQ 57 DQ 58 DQ 26 DQ 59 DQ 27 VCC Vcc DQ 60 DQ 28 DQ 61 DQ 29 DQ 62 DQ 30 DQ 63 DQ 31 Vss Vss SCL SDA VCC Vcc
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A8] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63 CLK0, CLK1 CKE0, CKE1 /CS0, /CS1 /RAS /CAS /WE SDA SCL VCC VSS NC : Data Inputs/Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : No Connection
DQMB0 - DQMB7 : DQ Mask Enable
Data Sheet M14014EJ5V0DS00
3
MC-4516CD641ES, 4516CD641PS
Block Diagram
CKE1 CKE0 /CS1 /CS0 DQMB0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 UDQM /CS CKE DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 LDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 D0 LDQM /CS CKE DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 UDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D4 DQMB1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQMB5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 UDQM /CS CKE DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 LDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 D2 LDQM /CS CKE DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 UDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D6
DQMB2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQMB6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
UDQM /CS CKE DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 LDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 D1
LDQM /CS CKE DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 UDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D5
DQMB3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 DQMB7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
UDQM /CS CKE DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 LDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 D3
LDQM /CS CKE DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 UDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D7
SERIAL PD SCL A0 A1 A2 SDA
VCC C VSS CLK0 CLK1 /RAS
D0 - D7 D0 - D7 CLK : D0 - D3 CLK : D4 - D7 /RAS : D0 - D7 /CAS : D0 - D7 /WE : D0 - D7
A0 - A11 BA0 BA1
A0 - A11 : D0 - D7 A13 : D0 - D7 A12 : D0 - D7
/CAS /WE
Remarks 1. D0 - D7: PD45128163 (2M words x 16 bits x 4 banks) 2. The value of all resistors is 10 . 4
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 8 0 to +70 -55 to +125 Unit V V mA W C C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 + 0.8 70 Unit V V V C
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 Data input/output capacitance CI/O Test condition A0 - A11, BA0(A13), BA1(A12), /RAS, /CAS, /WE CLK0, CLK1 CKE0, CKE1 /CS0, /CS1 DQMB0 - DQMB7 DQ0 - DQ63 MIN. 30 23 18 18 7 9 TYP. MAX. 60 37 30 30 14 18 pF Unit pF
Data Sheet M14014EJ5V0DS00
5
MC-4516CD641ES, 4516CD641PS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current Symbol ICC1 Test condition Burst length = 1, tRC tRC(MIN.) /CAS latency = 2 -A80 -A10 /CAS latency = 3 -A80 -A10 Precharge standby current in ICC2P ICC2PS ICC2N CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns. ICC2NS Active standby current in power down mode Active standby current in non power down mode ICC3NS Operating current (Burst mode) /CAS latency = 3 ICC4 ICC3P ICC3PS ICC3N CKE VIH(MIN.), tCK = , Input signals are stable. CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns. CKE VIH(MIN.), tCK = , Input signals are stable. tCK tCK(MIN.), IO = 0 mA /CAS latency = 2 -A80 -A10 -A80 -A10 160 700 560 820 680 1,040 1,040 1,040 1,040 16 -8 -3 2.4 0.4 +8 +3 mA mA 3 mA 2 64 40 32 240 mA mA MIN. MAX. 560 560 560 560 8 8 160 mA mA Unit mA Notes 1
5
power down mode Precharge standby current in non power down mode
5 CBR (Auto) refresh current
ICC5
tRC tRC(MIN.)
/CAS latency = 2
-A80 -A10
/CAS latency = 3
-A80 -A10
5
Self refresh current Input leakage current Output leakage current High level output voltage Low level output voltage
ICC6 II(L) IO(L) VOH VOL
CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V DOUT is disabled, VO = 0 to 3.6 V IO = - 4.0 mA IO = + 4.0 mA
A A
V V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
6
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
5 Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level Value 2.4 / 0.4 1.4 1 1.4 Unit V V ns V
tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH Output tCL
Input
Data Sheet M14014EJ5V0DS00
7
MC-4516CD641ES, 4516CD641PS
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time
/CAS latency = 3 /CAS latency = 2
-A80 MAX. (125 MHz) (100 MHz) 6 6 3 3 3 0 3 3 2 1 2 1 2 1 2 2 1 6 6 3 3 3 0 3 3 2 1 2 1 2 1 2 2 1 MIN. 10 13
-A10 MAX. (100 MHz) (77 MHz) 6 7
Unit
Note
tCK3 tCK2 tAC3 tAC2 tCH tCL tOH tLZ
8 10
ns ns ns ns ns ns ns ns 1 1 1
Access time from CLK
/CAS latency = 3 /CAS latency = 2
CLK high level width CLK low level width Data-out hold time Data-out low-impedance time Data-out high-impedance time
/CAS latency = 3 /CAS latency = 2
tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS tCMH
6 7
ns ns ns ns ns ns ns ns ns ns ns
Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS0, /CS1, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time Command (/CS0, /CS1, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time
Note 1. Output load
Z = 50 Output 50 pF
Remark These specifications are applied to the monolithic device.
8
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (Operation) REF to REF/ACT command period (Refresh) ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command period (Auto precharge) Mode register set cycle time Transition time Refresh time (4,096 refresh cycles)
/CAS latency = 3 /CAS latency = 2
-A80 MAX. MIN. 70 78 120,000 50 20 20 20 10
-A10 MAX.
Unit
Note
tRC tRC1 tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF
70 70 48 20 20 16 8 1CLK+20 1CLK+20 2 0.5 30 64
ns ns 120,000 ns ns ns ns ns ns ns CLK 30 64 ns ms
1CLK+20 1CLK+20 2 1
Data Sheet M14014EJ5V0DS00
9
MC-4516CD641ES, 4516CD641PS
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface CL = 3 Cycle time -A80 -A10 10 CL =3 Access time -A80 -A10 11 12 13 14 15 16 17 18 19 20 21 22 23 DIMM configuration type Refresh rate/type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 Cycle time -A80 -A10 24 CL = 2 Access time -A80 -A10 25-26 27 tRP(MIN.) -A80 -A10 28 tRRD(MIN.) -A80 -A10 29 tRCD(MIN.) -A80 -A10 30 tRAS(MIN.) -A80 -A10 31 Module bank density Hex 80H 08H 04H 0CH 09H 02H 40H 00H 01H 80H A0H 60H 60H 00H 80H 10H 00H 01H 8FH 04H 06H 01H 01H 00H 0EH A0H D0H 60H 70H 00H 14H 14H 10H 14H 14H 14H 30H 32H 10H Bit 7 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 Bit 3 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 Bit 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 ns 20 ns 16 ns 20 ns 20 ns 20 ns 48 ns 50 ns 64M bytes 10 ns 13 ns 6 ns 7 ns
(1/2)
Notes 128 bytes 256 bytes SDRAM 12 rows 9 columns 2 banks 64 bits 0 LVTTL 8 ns 10 ns 6 ns 6 ns None Normal x16 None 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0
10
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
(2/2)
Byte No. 32 Function Described Command and address signal setup time 33 Command and address signal hold time 34 Data signal input setup time -A80 -A10 -A80 -A10 -A80 -A10 35 Data signal input hold time -A80 -A10 36-61 62 SPD revision -A80 -A10 63 Checksum for bytes 0 - 62 64-71 72 73-90 91-92 93-94 95-98 99-125 126 Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date Assembly serial number Mfg specific Intel specification frequency -A80 -A10 127 Intel specification /CAS latency support -A80 -A10 64H 64H C7H C5H 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 100 MHz 100 MHz -A80 -A10 Hex 20H 20H 10H 10H 20H 20H 10H 10H 00H 12H 12H E8H 4EH Bit 7 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 6 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit 5 1 1 0 0 1 1 0 0 0 0 0 1 1 Bit 4 0 0 1 1 0 0 1 1 0 1 1 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit 2 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 1 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.2 A 1.2 A Notes 2 ns 2 ns 1 ns 1 ns 2 ns 2 ns 1 ns 1 ns
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
Data Sheet M14014EJ5V0DS00
11
MC-4516CD641ES, 4516CD641PS
5 Package Drawings
[MC-4516CD641ES]
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) M1 (AREA B) R Q M L Y Z N
M2 (AREA A)
H C
A
S
(OPTIONAL HOLES)
U1
U2 T
I
B D A1 (AREA A)
E
F
ITEM A A1 B C D D1 D2 E F H I L M M1 M2
MILLIMETERS 67.6 67.60.15 23.2 29.0 4.6 1.50.10 4.0 32.8 3.7 0.8 (T.P.) 3.3 20.0 31.750.15 9.75 22.0 3.8 MAX. R2.0 4.000.10
detail of A part W D2
D1 V
X
N Q R S T U1 U2 V W X Y Z
1.8
1.00.1 3.2 MIN. 4.0 MIN. 0.25 MAX. 0.60.05 2.55 MIN. 2.0 MIN. 2.0 MIN. M144S-80A14
12
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
[MC-4516CD641PS]
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) M1 (AREA B) R Q M L Y Z N
M2 (AREA A)
H C
A
S
(OPTIONAL HOLES)
U1
U2 T
I
B D A1 (AREA A)
E
F
ITEM A A1 B C D D1 D2 E F H I L M M1 M2
MILLIMETERS 67.6 67.60.15 23.2 29.0 4.6 1.50.10 4.0 32.8 3.7 0.8 (T.P.) 3.3 20.0 31.750.15 9.75 22.0 3.8 MAX. R2.0 4.000.10
detail of A part W D2
D1 V
X
N Q R S T U1 U2 V W X Y Z
1.8
1.00.1 3.2 MIN. 4.0 MIN. 0.25 MAX. 0.60.05 2.55 MIN. 2.0 MIN. 2.0 MIN. M144S-80A16
Data Sheet M14014EJ5V0DS00
13
MC-4516CD641ES, 4516CD641PS
[MEMO]
14
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M14014EJ5V0DS00
15
MC-4516CD641ES, 4516CD641PS
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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